Methods for moving blocks of data around data processing systems have been in existence for a number of decades. In large scale data processing systems, such data transfers are accomplished on a regular basis through bus or other interconnection arrangements. Such systems easily accommodate large blocks of data and are able to handle them rapidly on a pipeline basis, without significantly slowing overall operations. It is desirable to accomplish the same type of transfer in a personal computer (PC) or a system of PC's, but often their designs do not render themselves amenable to such operations. Of necessity, PC's are more limited in capability and function. This does not, however, inhibit the user from demanding ever increasing levels of performance from their units. This is especially true with respect to PC's used to drive sophisticated graphics display units.
PC memories are often not designed to interface easily with sophisticated graphic display units. For instance, many PC random access memories (RAM) are organized on a bit-planar basis with the respective bits of a byte or word resident in a plurality of planes in corresponding bit positions. While such PC/RAM organizations are useful for data processing applications where predetermined blocks of data are accessed and handled, when it is necessary to access a block of data, where the block may have any starting point and any end point, and to transfer such block of data into a memory at a starting point chosen by the user, such an operation can be accomplished, but only relatively slowly.
Block data transfers are encountered in display applications where it is desirable to insert, in a display memory, a block of new data (e.g., insertion of a window of new data in a preexisting display). In those cases, the system must access a data unit corresponding to a first picture element (PEL) and then continue accessing data units until the last PEL is retrieved. The accessed data units must be aligned so that they are properly justified when inserted in the display memory. This allows optimum use of the display memory data capacity. Additionally, many PC RAMS are accessible on only a byte or larger data unit basis, so if the initial PEL starts in the interior of a byte, the PEL must be extracted from the byte, aligned and then transferred. All of this is preferably done with a minimum number of memory accesses to avoid the delay inherent therein.
Others have coped with such display-related data transfers in various ways. In U.S. Pat. No. 3,938,102 to Morrin et al, a system is described which accomplishes a 1-to-1 mapping between pq subarrays of points from an array of rspq points in an all-points addressable memory to a word organized RAM of pq modules. Only 1 point in each of the pq modules is accessible during a single memory cycle.
Belser, in U.S. Pat. No. 3,973,245, discloses a method for converting a vector-coded sub-array into a linear array which is suitable for raster display. Each line segment is represented by a sequence of X, Y coordinate values. A formatter, in response to the vector information, formats the vector data into an area word (an array of data points). This information is used to drive a raster display system.
In U.S. Pat. No. 4,434,502 to Arakawa, a system is shown for accessing display data distributed among four independent memories or blocks. This is accomplished by modifying an input address to arithmetically produce a plurality of addresses which are used to address a plurality of separate memory blocks. The memory block outputs pass through a selection/alignment matrix circuit which selects from the outputs of the memory blocks only those bytes in a desired block of data and aligns them into an array.
Accordingly, it is an object of this invention to provide a method and means for block data transfers when the blocks of data have variable starting and ending points.
It is another object of this invention to provide a rapid method and means for block data transfers of non-aligned data between memories.
A further object of this invention is to provide a rapid method and means for non-aligned data transfers wherein such transfers must pass through a restricting buffer system.